1. Technical Field
The present invention relates to a semiconductor device or the like in which a plurality of MOS (Metal Oxide Semiconductor) field-effect transistors or LD (Lateral Double-diffused) MOS field-effect transistors are provided together on the same substrate.
2. Related Art
Generally, in the case of constituting an electronic circuit by providing a plurality of MOS field-effect transistors or LDMOS field-effect transistors together on the same semiconductor substrate, the potential of a semiconductor substrate of a first conductivity type is taken as a reference potential (0V), and a potential that is either positive or negative relative to the reference potential is supplied to wells of a second conductivity type in which the transistors are formed.
For example, in the case where a P-type semiconductor substrate is used, the potential of the P-type semiconductor substrate is taken as the reference potential (0V), and a positive potential is supplied to an N-well provided in the P-type semiconductor substrate to reverse bias the P-N junction. Current can thereby be prevented from flowing toward the N-well from the P-type semiconductor substrate. Also, in the case where a plurality of N-wells are provided within the P-type semiconductor substrate, it is possible to supply respectively different potentials to the plurality of N-wells, but these potentials must be positive potentials.
As related technology, JP-A-2003-60071 (paras. 0018-0020, FIG. 1) discloses a semiconductor integrated circuit device having an SRAM that is able to reduce the number of grounding taps per cell, while providing a buried impurity layer as a countermeasure against alpha-ray soft error. This semiconductor integrated circuit device includes a buried impurity layer of the second conductivity type arranged as an intermediate layer in a semiconductor substrate of the first conductivity type, a well region of the first conductivity type provided with a predetermined depth in the semiconductor substrate without contacting the buried impurity layer, a well region of the second conductivity type provided with a predetermined depth in the semiconductor substrate without contacting the buried impurity layer, and an integrated circuit element provided in the first conductivity type well region and an integrated circuit element provided in the second conductivity type well region that relate to each other.
Referring to FIG. 1 of JP-A-2003-60071, a ground potential VSS is supplied to a P-type semiconductor substrate that is located between an N-type buried impurity layer and P-well and N-well regions. The P-well region can thereby be prevented from floating, in a state where the buried impurity layer is provided as countermeasure against soft error. On the other hand, a positive power potential VDD is supplied to the N-well region. Accordingly, the transistors that are formed in the P-well region and the N-well region operate in a voltage range between the ground potential VSS and the power potential VDD.
However, there are cases where a transistor that operates in a voltage range at or above the reference potential and a transistor that operates in a voltage range at or below the reference potential are both used, depending on the electronic circuit. In such cases, it is desirable to constitute the electronic circuit by providing both transistors together on the same semiconductor substrate.